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cdk3405 8-bit, 180msps, triple video dacs rev 1b data sheet ?2009-2010 cadeka microcircuits llc www.cadeka.com cdk3405 8-bit, 180msps, triple video dacs f e a t u r e s n 8-bit resolution, 180msps n 2.5% gain matching n 0.5% linearity error n sync and blank controls n 1.0v pp video into 37.5 or 75 load n internal bandgap voltage reference n low glitch energy n single +3.3v power supply a p p l i c a t i o n s n video signal conversion C rgb C yc b c r C composite, y, c n multimedia systems n image processing n pc graphics general description cdk3405 is a low-cost triple d/a converter that is tailored to ft graphics and video applications where speed is critical. cmos-level inputs are converted to analog current outputs that can drive 25-37.5 loads corresponding to doubly-terminated 50-75 loads. a sync current following sync input timing is added to the io g output. blank will override rgb inputs, setting io g , io b and io r currents to zero when blank = l. although appropriate for many applications, the internal 1.25v reference voltage can be overridden by the v ref input. few external components are required, just the current reference resistor, current output load resistors, bypass capacitors, and decoupling capacitors. package is a 48-lead tqfp. fabrication technology is cmos. performance is guaranteed from -40c to +125c. block diagram ordering information part number package pb-free rohs compliant operating temp range packaging method package quantity CDK3405ATQ48 tqfp-48 yes yes -40c to +125c tray 250 CDK3405ATQ48y tqfp-48 yes yes -40c to +125c tray 1,250 moisture sensitivity level for all parts is msl-3. 8-bit d/a converter 8 sync clock g7-0 comp +1.25v ref io g blank 8-bit d/a converter 8 b7-0 io b 8-bit d/a converter 8 r7-0 io r ref ref sync r v
?2009-2010 cadeka microcircuits llc www.cadeka.com 2 data sheet cdk3405 8-bit, 180msps, triple video dacs rev 1b pin confguration tqfp-48 gnd gnd g0 g1 g2 g3 g4 g5 g6 g7 sync gnd gnd r set v ref comp io r io g nc nc v aa v aa io b nc gnd r7 r6 r5 r4 r3 r2 r1 r0 v aa gnd gnd b0 b1 b2 b4 b3 clock 1 2 3 4 5 6 7 8 9 10 blank 11 12 36 35 34 33 32 31 30 29 28 27 gnd 26 25 13 14 15 16 17 18 19 20 21 22 b5 b6 b7 23 24 48 47 46 45 44 43 42 41 40 39 nc 38 37 tqfp cdk3405 pin assignments pin no. pin name description clock and pixel i/o 24 clk clock input 41-48 r7-0 red pixel data inputs 3-10 g7-0 green pixel data inputs 16-23 b7-0 blue pixel data inputs controls 12 sync sync pulse input 11 blank blanking input video outputs 34 ior red current output 32 iog green current output 28 iob blue current output voltage reference 36 v ref input for dacs or voltage reference output (1.25v) 37 r set current-setting resistor 35 comp compensation capacitor power and ground 13, 29, 30 v aa analog power supply 1, 2, 14, 15, 25, 26, 39, 40 gnd ground 27, 31, 33 nc no connect
?2009-2010 cadeka microcircuits llc www.cadeka.com 3 data sheet cdk3405 8-bit, 180msps, triple video dacs rev 1b absolute maximum ratings the safety of the device is not guaranteed when it is operated above the absolute maximum ratings. the device should not be operated at these absolute limits. adhere to the recommended operating conditions for proper device function. the information contained in the electrical characteristics tables and typical performance plots refect the operating conditions noted on the tables and plots. parameter min max unit power supply voltage v aa (measured to gnd) -0.5 4.0 v digital inputs applied voltage (measured to gnd) (2) -0.5 v aa + 0.5 v forced current (3,4) -5.0 5.0 ma analog inputs applied voltage (measured to gnd) (2) -0.5 v aa + 0.5 v forced current (3,4) -10.0 10.0 ma analog outputs applied voltage (measured to gnd) (2) -0.5 v aa + 0.5 v forced current (3,4) -60.0 60.0 ma short circuit duration (single output in high state to gnd) unlimited sec reliability information parameter min max unit temperature operating, ambient -40 125 c junction 150 c lead soldering (10 seconds) 300 c vapor phase soldering (1 minute) 220 c storage -65 150 c package thermal resistance ( ja ) 65 c/w notes: 1. functional operation under any of these conditions is not implied. performance and reliability are guaranteed only if operating conditions are not exceeded. 2. applied voltage must be current limited to specifed range. 3. forcing voltage must be limited to specifed range. 4. current is specifed as conventional current fowing into the device. esd protection parameter tqfp-48 human body model (hbm) tbd charged device model (cdm) tbd recommended operating conditions symbol parameter min typ max unit v aa power supply voltage 3.0 3.3 3.6 v v ref reference voltage, external 1.0 1.25 1.5 v c c compensation capacitor 0.1 f r l output load 37.5 t a ambient temperature, still air -40 +125 c 0 0.5 1 1.5 2 2.5 3 -40 -20 0 20 40 60 80 100 120 maximum power dissipation (w) ambient temperature (c) tqfp-48 cdk3405 power derating
?2009-2010 cadeka microcircuits llc www.cadeka.com 4 data sheet cdk3405 8-bit, 180msps, triple video dacs rev 1b electrical characteristics (t a = 25c, v aa =3.3v, v ref = 1.25v, r l = 37.5, unless otherwise noted) symbol parameter conditions min typ max units i dd power supply current t a = 25c (1) 80 85 ma t a = -40c to +125c (2) 95 ma pd total power dissipation (2) t a = -40c to +125c 300 mw digital inputs v ih input voltage, high (1) t a = -40c to +125c 2.5 v v il input voltage, low (1) t a = -40c to +125c 0.8 v i ih input current, high (1) t a = -40c to +125c -1 1 a i il input current, low (1) t a = -40c to +125c -1 1 a c i input capacitance 4 pf analog outputs output current (1) 30 ma r o output resistance 40 k c o output capacitance 7 pf reference output v ref reference voltage output (1) t a = -40c to +125c 1.135 1.25 1.365 v notes: 1. 100% tested at 25c. 2. parameter is guaranteed (but not tested) by design and characterization data. switching characteristics (t a = 25c, v aa =3.3v, v ref = 1.25v, r l = 37.5, unless otherwise noted) symbol parameter conditions min typ max units clock input conversion rate (1) t a = -40c to +125c 180 msps t pwh pulse-width high (2) t a = -40c to +125c 2 ns t pwl pulse-width low (2) t a = -40c to +125c 2 ns data inputs t s setup t a = 25c (1) 1.5 ns t a = -40c to +125c (2) 2 ns t h hold t a = 25c (1) 0.6 ns t a = -40c to +125c (2) 0.6 ns data outputs, with 50 doubly terminated load t d clock to output delay t a = -40c to +125c 1.6 ns t r output risetime t a = -40c to +125c 0.6 ns t f output falltime t a = -40c to +125c 0.4 ns t set settling time 2.5 ns t skew output skew 0.3 ns notes: 1. 100% production tested at +25c. 2. parameter is guaranteed (but not tested) by design and characterization data.
?2009-2010 cadeka microcircuits llc www.cadeka.com 5 data sheet cdk3405 8-bit, 180msps, triple video dacs rev 1b dc performance (t a = 25c, v aa =3.3v, v ref = 1.25v, r l = 37.5, unless otherwise noted) symbol parameter conditions min typ max units resolution 8 bits inl integral linearity error t a = 25c (1) -0.5 0.5 lsb t a = -40c to +125c (2) -0.5 0.5 lsb dnl differential linearity error t a = 25c (1) -0.5 0.5 lsb t a = -40c to +125c (2) -0.5 0.5 lsb offset error t a = -40c to +125c (2) 0.01 %fs gain matching error t a = -40c to +125c (1) -2.5 2.5 %fs absolute gain error t a = -40c to +125c (1) -3.5 3.5 %fs full-scale output current t a = 25c (1) 18.0 18.7 19.4 ma t a = -40c to +125c (2) 18.0 18.7 19.4 ma t a = -40c to +125c , with internal reference. trim rset to calibrate full-scale current. 18.7 ma psrr power supply rejection ratio t a = -40c to +125c (2) -0.01 0 0.01 %/% notes: 1. 100% production tested at +25c. 2. parameter is guaranteed (but not tested) by design and characterization data. ac performance (t a = 25c, v aa = 3.3v, v ref = 1.25v, r l = 37.5, unless otherwise noted) symbol parameter conditions min typ max units analog outputs glitch energy 20 pvsec dac-to-dac crosstalk 30 db data feedthrough 50 db clock feedthrough 60 db notes: 1. 100% production tested at +25c. 2. parameter is guaranteed (but not tested) by design and characterization data.
?2009-2010 cadeka microcircuits llc www.cadeka.com 6 data sheet cdk3405 8-bit, 180msps, triple video dacs rev 1b rgb7-0 (msblsb) blue and red green sync blank v out (v) sync blank v out (v) 1111 1111 1 1 0.700 1 1 1.007 1111 1111 0 1 0.700 0 1 0.700 1111 1110 1 1 0.697 1 1 1.004 1111 1101 1 1 0.695 1 1 1.001 ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1000 0000 1 1 0.351 1 1 0.658 0111 1111 1 1 0.349 1 1 0.656 0111 1111 0 1 0.349 0 1 0.349 ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 0010 1 1 0.005 1 1 0.312 0000 0001 1 1 0.003 1 1 0.310 0000 0000 1 1 0.000 1 1 0.307 0000 0000 0 1 0.000 0 1 0.000 xxxx xxxx 1 0 0.000 1 0 0.307 xxxx xxxx 0 0 0.000 0 0 0.000 table 1. output voltage vs. input code, sync and blank , v ref = 1.25v, r ref = 348, r l = 37.5 clk pixel data and controls output data n+2 data n+1 data n t pwl t s t h 50% 3%/fs 90% 10% t f t r t pwh 1/f s t d t set figure 1. cdk3405 timing diagram
?2009-2010 cadeka microcircuits llc www.cadeka.com 7 data sheet cdk3405 8-bit, 180msps, triple video dacs rev 1b functional description within the cdk3405 are three identical 8-bit d/a converters, each with a current source output. external loads are required to convert the current to voltage outputs. data inputs rgb7-0 are overridden by the blank input. sync = h activates, sync current from i os for sync-on-green video signals. figure 2. cdk3405 current source structure digital inputs incoming gbr data is regsitered on the rising edge of the clock input, clk. analog outputs follow the rising edge of clk after a delay, t do . clock input - clk pixel data is registered on the rising edge of clk. clk should be driven by a dedicated buffer to avoid refection induced jitter, overshoot, and undershoot. pixel data inputs - r7-0, b7-0, g7-0 rgb digital inputs are registered on the rising edge of clk. sync and blank sync and blank inputs control the output level (figure 3 and table 1, on the previous page) of the d/a convert - ers during crt retrace intervals. blank forces the d/a outputs to the blanking level while sync = l turns off a current source, i os , that is connected to the green d/a converter. sync = h adds a 112/256 fraction of full-scale current to the green output. sync = l extinguishes the sync current during the sync tip. blank gates the d/a inputs. if blank = high, the d/a inputs control the output currents to be added to the out - put blanking level. if blank = low, data inputs and the pedestal are disabled. data: 660mv max. pedestal: 54mv sync: 286mv figure 3. normal output levels sync pulse input - sync bringing sync low, disables a current source which su - perimposes a sync pulse on the io g output. sync and pixel data are registered on the rising edge of clk. sync does not override any other data and should be used only during the blanking interval. if sync pulses are not re - quired, sync should be connected to gnd. blanking input - blank when blank is low, pixel data inputs are ignored and the d/a converter outputs are driven to the blanking level. blank is registered on the rising edge of clk. d/a outputs each d/a output is a current source from the v dda supply. expressed in current units, the gbr transformation from data to current is as follows: g = g7-0 & blank + sync * 112 b = b7-0 & blank r = r7-0 & blank typical lsb current step is 73.2a. to obtain a voltage output, a resistor must be connected to ground. output voltage depends upon this external resistor, the reference voltage, and the value of the gain-setting resistor con - nected between r ref and gnd. to implement a doubly-terminated 75 transmission line, a shunt 75 resistor should be placed adjacent to the analog output pin. with a terminated 75 line connected to the analog output, the load on the cdk3405 current source is 37.5. v dda sync v dda v dda g7-0 b7-0 v dda r7-0 i os v aa v aa v aa v aa
?2009-2010 cadeka microcircuits llc www.cadeka.com 8 data sheet cdk3405 8-bit, 180msps, triple video dacs rev 1b the cdk3405 may also be operated with a single 75 terminating resistor. to lower the output voltage swing to the desired range, the nominal value of the resistor on r ref should be doubled. r, g, and b current outputs - io r , io g , io b current source outputs can drive vesa vsis, and rs- 343a/smpte-170m compatible levels into doubly-termi - nated 75 lines. sync pulses can be added to the green output. when sync is high, the current added to io g is: io s = 2.33 (v ref / r ref ) current-setting resistor - r ref full-scale output current of each d/a converter is deter - mined by the value of the resistor connected between r ref and gnd. nominal value of r ref is found from: r ref = 5.31 (v ref /i fs ) where i fs is the full-scale (white) output current (in amps) from the d/a converter (without sync). sync is 0.439 * i fs . d/a full-scale (white) current may also be calculated from: i fs = v fs /r l where v fs is the white voltage level and r l is the total resistive load () on each d/a converter. v fs is the blank to full-scale voltage. voltage reference full scale current is a multiple of the current i set through an external resistor, r set connected between the r ref pin and gnd. voltage across r set is the reference voltage, v ref, which can be derived from either the 1.25 volt in - ternal bandgap reference or an external voltage reference connected to v ref . to minimize noise, a 0.1f capacitor should be connected between v ref and ground. i set is mirrored to each of the gbr output current sources. to minimize noise, a 0.1f capacitor should be connected between the comp pin and the analog supply voltage v aa . voltage reference output/input - v ref an internal voltage source of +1.25v is output on the v ref pin. an external +1.25v reference may be applied to over - ride the internal reference. decoupling v ref to gnd with a 0.1f ceramic capacitor is required. power and ground required power is a single +3.3v supply. to minimize power supply induced noise, analog +3.3v should be connected to all three supply pins with 0.1f and 0.01f decoupling capacitors placed adjacent to each v aa pin or pin pair. the high slew-rate of digital data makes capacitive cou - pling to the outputs of any d/a converter a potential problem. since the digital signals contain high-frequency components of the clk signal, as well as the video out - put signal, the resulting data feedthrough often looks like harmonic distortion or reduced signal-to-noise perfor - mance. all ground pins should be connected to a common solid ground plane for best performance.
?2009-2010 cadeka microcircuits llc www.cadeka.com 9 data sheet cdk3405 8-bit, 180msps, triple video dacs rev 1b applications dicussion figure 9 (on the following page) illustrates a typical cdk3405 interface circuit. in this example, an optional 1.2v band - gap reference is connected to the v ref output, overriding the internal voltage reference source. grounding it is important that the cdk3405 power supply is well- regulated and free of high-frequency noise. careful power supply decoupling will ensure the highest quality video signals at the output of the circuit. the cdk3405 has separate analog and digital circuits. to keep digital system noise from the d/a converter, it is recommended that power supply voltages come from the system analog power source and all ground connections (gnd) be made to the analog ground plane. power supply pins should be indi - vidually decoupled at the pin. printed circuit board layout designing with high-performance mixed-signal circuits demands printed circuits with ground planes. overall system performance is strongly infuenced by the board layout. capacitive coupling from digital to analog circuits may result in poor d/a conversion. consider the following suggestions when doing the layout: 1. keep the critical analog traces (v ref , i ref , comp, io s , io r , io g ) as short as possible and as far as possible from all digital signals. the cdk3405 should be located near the board edge, close to the analog out-put connectors. 2. the power plane for the cdk3405 should be separate from that which supplies the digital circuitry. a single power plane should be used for all of the v aa pins. if the power supply for the cdk3405 is the same as that of the systems digital circuitry, power to the cdk3405 should be decoupled with 0.1f and 0.01f capacitors and isolated with a ferrite bead. 3. the ground plane should be solid, not cross-hatched. connections to the ground plane should have very short leads. 4. if the digital power supply has a dedicated power plane layer, it should not be placed under the cdk3405, the voltage reference, or the analog outputs. capacitive coupling of digital power supply noise from this layer to the cdk3405 and its related analog circuitry can have an adverse effect on performance. 5. clk should be handled carefully. jitter and noise on this clock will degrade performance. terminate the clock line carefully to eliminate overshoot and ringing. improved transisiton times output shunt capacitance dominates slowing of output transition times, whereas series inductance causes a small amount of ringing that affects overshoot and settling time. with a doubly terminated 75 load, transition times can be improved by matching the capacitive impedance output of the cdk3405. output capacitance can be matched with a 220nh inductor in series with the 75 source termination. figure 4. schematic, transition time sharpening circuit a 220nh inductor trims the performance of a 4ft cable, quite well. in figures 5 through 8, the glitch at 12.5ns, is due to a refection from the source. not shown, are smaller glitches at 25 and 37.5ns, corresponding to secondary and tertiary refections. inductor values should be selected to match the length and type of the cable. u 1 cdk3405 3 2 r 1 7 5? w 1 c o a x w 2 c o a x w 3 c o a x l 1 2 20 n h l 2 2 20 n h l 3 2 20 n h r 2 7 5? r 3 7 5? r 4 7 5? r 5 7 5? r 6 7 5? 2 9 3 3 io g io b io r
?2009-2010 cadeka microcircuits llc www.cadeka.com 10 data sheet cdk3405 8-bit, 180msps, triple video dacs rev 1b figure 5. unmatched t r figure 6. matched t r figure 7. unmatched t f figure 8. matched t f -5 0 5 10 15 20 0.8 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 time (ns) r out (v) -5 0 5 10 15 20 0.8 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 time (ns) g out (v) -5 0 5 10 15 20 0.8 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 time (ns) g out (v) -5 0 5 10 15 20 0.8 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 time (ns) g out (v) figure 9. typical interface circuit diagram evaluation boards are available (ceb3405), contact cadeka for more information. related products n cdk3400/3401 triple 10-bit 180msps dacs n cdk3404 triple 8-bit 180msps dac r7-0 g7-0 b7-0 cdk3405 triple 8-bit d/a converter clk sync blank red pixel input green pixel input blue pixel input clock sync blank comp v ref r ref v dda 0.1f 0.1f 348? 3.3k? (not required without external reference) lm185-1.2 (optional) io r io g io b 75? 75? 75? 75? 75? 75? z o = 75? red green w/sync blue z o = 75? z o = 75? +3.3v 0.01 f 0.1f 0.1f 10f vddd gnd vdda v aa v aa (29, 30) (13) v aa
for additional information regarding our products, please visit cadeka at: cadeka.com cadeka, the cadeka logo design, comlinear and the comlinear logo design are trademarks or registered trademarks of cadeka microcircuits llc. all other brand and product names may be trademarks of their respective companies. cadeka reserves the right to make changes to any products and services herein at any time without notice. cadeka does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by cadeka; nor does the purchase, lease, or use of a product or service from cadeka convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of cadeka or of third parties. copyright ?2009-2010 by cadeka microcircuits llc. all rights reserved. cadeka headquarters loveland, colorado t: 970.663.5452 t: 877.663.5452 (toll free) data sheet cdk3405 8-bit, 180msps, triple video dacs rev 1b mechanical dimensions tqfp-48 package

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